The art of isolating semiconductor devices becomes one important aspect of modem metal-oxide-semiconductor (MOS) and bipolar integrated Circuit technology. With increasing densities of up to hundreds of thousands of devices on a single chip, improper isolation among devices will cause current leakages. These current leakages can consume significant amounts of power. In addition, improper isolation between devices can exacerbate latchup, which can damage the circuit temporarily or permanently. Still further, improper isolation can result in noise margin degradation, voltage shift or crosstalk.
In MOS technology, isolation is usually practiced by forming isolation regions between neighboring active regions. Typically, an isolation region is formed by ion-implanting a channel stop layer of polarity opposite to the source electrode and the drain electrode of the integrated circuit device, and growing a thick oxide, often referred to as field oxide (FOX). The channel stop and the FOX cause the threshold voltage in the isolation region to be much higher than those of the neighboring active devices, making surface inversion not likely to occur under the field oxide region.
The local oxidation of silicon (LOGOS) method is also widely used to isolate active regions in silicon. In LOCOS technology, a silicon nitride layer is used as an efficient oxidation mask which prevents the oxidants from reaching the silicon surface covered by silicon nitride. In addition, the silicon nitride layer oxidizes very slowly compared to silicon. However, direct deposition of silicon nitride on silicon can cause stress induced defects when the structure is subjected to oxidation at elevated temperature. These defects can be considerably reduced by forming a thin (100.about.500 angstroms) pad oxide layer between the silicon and the silicon nitride. The pad oxide reduces the force transmitted to the silicon by relieving the stress. It thus acts as a buffer which cushions the transmission of stress between the silicon and the silicon nitride.
Unfortunately, the pad oxide layer provides a lateral path for oxidation of silicon. This lateral extension of oxidation through pad oxide is frequently referred to as a "bird's beak" because of its form. The extent of the bird's beak can be reduced by decreasing the thickness of the pad oxide, which, however will cause more stress induced defects from the above silicon nitride layer. Therefore, the thickness of the pad oxide and the silicon nitride layer must be optimized to minimize the extent of the bird's beak without generating defects.
Several methods in the prior art have been designed for improving the LOCOS isolation process to minimize the bird's beak. For example, the sealed-interface local oxidation (SILO) process uses an additional thin silicon nitride over the silicon substrate followed by forming a pad oxide layer and then a thick silicon nitride layer. The SILO process can reduce the bird's beak, but at the expense of generating more stress, more crystal defects, and higher leakage currents. See pp. 554-561, of J. Hui, et al., "Sealed-interface local oxidation technology," IEEE Trans. Electron Devices, vol. ED-29, 1982.
Another improved LOCOS method, called buried oxide (BOX) process, has been devised which uses an aluminum mask to etch a silicon groove and then subsequently remove a plasma deposited silicon dioxide layer. The BOX process can effectively reduce the bird's beak, but at the expense of manufacture complexity. See pp. 384-387, of K. Kurosawa, et al., "A New Bird's Beak Free Field Isolation Technique for VLSI Devices," IEDM Tech. Dig., 1981.
Beside bird's beak effect, another important limitation is the sharp decrease in the field oxide thickness as the isolation spacing is reduced below 1 micrometer. The narrower the opening, the thinner the field oxide. This effect is frequently called field oxide thinning effect, and is more serious for deep sub-micron semiconductor devices. See p. 671, of A. Bryant, et al., "Characteristics of CMOS Device Isolation for the ULSI Age." IEDM, 1994.